Course Content

Compact and high-throughput parameterisable architectures for memory[1]based FFT algorithms

Abstract

Designers must carefully choose the best-suited fast Fourier transform (FFT) algorithm among various available techniques for the custom implementation that meets their design requirements, such as throughput, latency, and area. This article, to the best of authors' knowledge, is the first to present a compact and yet high-throughput parameterisable hardware architecture for implementing different FFT algorithms, including radix-2, radix-4, radix-8, mixed-radix, and split-radix algorithms. The designed architectures are fully parameterisable to support a variety of transform lengths and variable word-lengths. The FFT algorithms have been modelled and simulated in double-precision floating-point and fixed-point representations using authors' custom-developed library of numerical operations. The designed FFT architectures are modelled in Verilog hardware description language and their cycle-accurate and bit-true simulation results are verified against their fixed-point simulation models. The characteristics and implementation results of various FFT architectures on a Xilinx Virtex-7 FPGA are presented. Compared to recently published works, authors' memory-based FFT architectures utilise less reconfigurable resources while maintaining comparable or higher operating frequencies. The ASIC implementation results in a standard 45-nm CMOS technology are also presented for the designed memory-based FFT architectures. The execution times of FFTs on a workstation and a graphics processing unit are compared against authors' FPGA implementations.