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Design and Verification of APB Protocol by using System Verilog and Universal Verification Methodology

Design and Verification of APB Protocol by using System Verilog and Universal Verification Methodology

Price : 14000

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Course Duration
Approx 10

Course Price
₹ 14000

Course Level
Beginner

Course Content

Design and Verification of APB Protocol by using System Verilog and Universal Verification Methodology

Abstract

The huge progress of VLSI technology enables the integration of millions of transistor on a single chip called System on chip (SOC).The SOC (system on chip) uses AMBA (Advanced Microcontroller Bus Architecture) as on chip bus protocol. APB (Advanced Peripheral Bus) is one of components of AMBA bus Architecture. In this paper we present the total Design and Verification of AMBA-APB Protocol for SOC Applications. AMBA Bus basically has many components like AHB, ASB, AXI etc which are high performance bus used to interface with low performance bus like APB. APB uses low peripheral bandwidth and is used to connect with slaves like UART, TIMER, Keypad and INTERRUPT CONTROLLER etc. The traditional way of verification is simulation based. As the technology improved complexity of IC’s has been increased. Hence time spent in verification also been increased. This paper mainly focuses on design of APB protocol in Verilog and Verifying in two languages such as System Verilog and Universal Verification Methodology (UVM).

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