Course Content

Composite Field Arithematic Based S-Box For AES Algorithm

Abstract

Generally AES algorithm uses Substitution box which works with ROM based lookup tables. Using the rom based Look up table, there occurs a significant irreducible amount of delay in the gates as well as access paths. Different combinations of logic gates in the critical path can be employed to reduce the delay. This paper proposes new way to design a S-box which works on Composite Field arithmetic resulting in significant reduction in the area in w.r.t FPGA slices and reduction in both gate delay and combinational path delay. The proposed S-box is designed using Verilog HDL, simulated in Modelsim 6.4c and synthesized in Xilinx ISE 13.2.