Course Content

Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

Abstract

The aim of this device is to create an UART (Universal Asynchronous Receiver/Transmitter) chip on FPGA (Field-Programmable Gate Array) to be able to control (embedded) devices which has a serial interface. In this situation the FPGA acts as master and controls other slave devices. The challenge for this device is present in the fact for sending whole strings that can be interpreted by the slave device and to be able to control it as desired. Until now most of the UART chips cold be able to send 8 bits (1 Byte), which was not enough to control devices which needs at least a few Bytes of commands. The other challenge is that until now the FPGA was the slave and the PC was the master, this way the communication could be done only between the PC and the FPGA. The presented device will act now as master and will control other slave devices.